Giacinto Paolo Saggese
Giacinto Paolo Saggese
Biography
- Co-Founder & CTO @ Causify.AI
- Developing production-grade Causal AI systems at Causify.AI, combining Bayesian inference, knowledge graphs, and temporal machine learning for decision-making under uncertainty. Applications include predictive maintenance, failure prediction, demand forecasting, and energy optimization.
- 3x startup founder
- Adjunct Professor, Computer Science @ University of Maryland, College Park
- Industry experiences
- Tech: NVIDIA, Synopsys, Intel
- Finance: June, Teza, Engineers' Gate
- Expertise:
- Bayesian machine learning, LLMs, reasoning agents
- 20+ years building AI/ML systems, quant strategies, and high-performance software
- Been writing code almost every day for the last 35 years (see GitHub stats for the last few years)
Latest Papers
A Novel Module-Sign Low-Power Implementation for the DLMS Adaptive Filter With Low Steady-State Error
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IEEE Trans. Circuits Syst. I Regul. Pap.
Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements
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IEEE Trans. Circuits Syst. I Regul. Pap.
Automated Derivation of Application-Specific Error Detectors Using Dynamic Analysis
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IEEE Trans. Dependable Secur. Comput.
Dynamic Derivation of Application-Specific Error Detectors and their Implementation in Hardware
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Sixth European Dependable Computing Conference, EDCC 2006, Coimbra,
Portugal, 18-20 October 2006
Microprocessor Sensitivity to Failures: Control vs Execution and Combinational vs Sequential Logic
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2005 International Conference on Dependable Systems and Networks (DSN
2005), 28 June - 1 July 2005, Yokohama, Japan, Proceedings
An Architectural Framework for Detecting Process Hangs/Crashes
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Dependable Computing - EDCC-5, 5th European Dependable Computing Conference,
Budapest, Hungary, April 20-22, 2005, Proceedings
Hardware Support for High Performance, Intrusion- and Fault-Tolerant Systems
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23rd International Symposium on Reliable Distributed Systems (SRDS
2004), 18-20 October 2004, Florianpolis, Brazil
A tamper resistant hardware accelerator for RSA cryptographic applications
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J. Syst. Archit.